The password to unlock this document is “L302”
L302
10.4-14.4 Ghz Local Oscillator
Jim Muehlberg (jmuehlbe@nrao.edu) NRAO-Socorro
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Keywords: EVLA, Synthesizer, Local
Oscillator, Phase Detector, DDS |
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Author Signatures:
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Approved by:
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Released by:
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I. Change Record
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2 March 2005 |
JEM |
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TABLE OF CONTENTS
B. Detailed Functional Descriptions
D. Software
Control Description
A. List of Required Test equipment
A. L302 Monitor and Control Point
Definitions (Telnet session)
B. Frequently
Used Commands. (Telnet session)
D. Analog to Digital Converter
Channel Assignments
E. TLV2556 (11 Channel, 12 BIT,
Analog to Digital Converter) Control Lines
F. DAC716, 16 Bit Digital to analog
converter control lines.
G. MAX6629 Temperature Sensor Control
Lines
H. Atmel AT25256 256K Serial EEPROM
Control Lines
I. TLV5624 Texas Instruments 8 Bit D to
A Converter (AGC DAC)
K. Example of EEPROM stored Data (ASCII)
I.. Change
Record
II.. Specifications
A. Electrical
B. Mechanical
III.. Overview
A. General Description
B. Detailed Functional Descriptions
1. RF Signal Flow
C. MIB Interface
D. Software Control Description
1. Frequency Lock Routine
2. Dual DDS 7
E. Operator Screen
F. Technician Screen
G. Maintenance Screen
IV.. Maintenance
A. List of Required Test equipment
B. Procedure
1. General Checkout procedure
2. Calibration of AGC Loop
V.. Appendix
A. L302 Monitor and Control Point Definitions (Telnet
session)
1. L302 Monitor Points
2. L302 Control Points
B. Frequently Used Commands. (Telnet session)
C. MIB I/O 19
D. Analog to Digital Converter Channel Assignments
E. TLV2556 (11 Channel, 12 BIT, Analog to Digital
Converter) Control Lines
F. DAC716, 16 Bit Digital to analog converter control
lines.
G. MAX6629 Temperature Sensor Control Lines
H. Atmel AT25256 256K Serial EEPROM Control Lines
I.. TLV5624 Texas Instruments 8 Bit D to A Converter
(AGC DAC)
J.. AD9852 Analog Devices DDS
K. Example of EEPROM stored Data (ASCII)
VI.. L302
Photographs
VII. Index
LIST OF FIGURES
Figure 2 Telnet Session Screen
Figure 3 L302 Discrete (Miteq) RF Chassis
Figure 4 L302 RF (Production) Chassis
Figure 5 L302 Right Side, all versions
Figure 6 L302 Back Panel, production
Figure 1 Telnet Session Screen
Figure 2 L302 Discrete (Miteq) RF Chassis
Figure 3 L302 RF (Production) Chassis
Figure 4 L302 Right Side, all versions
Figure 5. 29
Figure 6 L302 Back Panel, production
LIST OF TABLES
Table 2 Analog to Digital Converter channels
Table 3 Monitor Analog to Digital Converter Control Lines
Table 4 Coarse Tuning Digital to Analog Converter Control
Lines
Table 5 Temperature Sensor Control Lines
Table
7 AGC D to A Converter Control Lines
Table
8 AD9852 DDS Control Lines
Table 1 I/O
Signal List
Table 2 Analog to Digital Converter channels
Table 3 Monitor Analog to Digital Converter Control
Lines
Table 4 Coarse Tuning Digital to Analog Converter
Control Lines
Table 5 Temperature Sensor Control Lines
Table 6 EEPROM Control Lines
Table 7.......................................................................................................................................................................................... 23
Table 8 AD9852 DDS Control Lines
II. Specifications
A. Electrical
Output frequency: 10.8-14.8 GHz nominal
Tuning Resolution: 1 uHz
Output Power: +13 dBm nominal
(programmableset)
Output phase noise :
1 Hz offset: tbddepends on reference noise
10 Hz offset: depends on reference noise
tbd
100 Hz offset: depends on reference noisetbd
1 kHz offset : depends on reference noisetbd
10 kHz offset: depends on reference noisetbd
100 kHz
offset: -115 107 dBc
1 MHz offset: >-120 dBc
Reference inputs : 128 MHz sine @ ~0 dBm, n*128 MHz from 10.752 GHz to 14.848 GHz @ ~-30dBm
Timing input : 19.2 Hz LVDS
Input power requirements
75 35 Watts nominal
+16.5
VDC @ tbd
1.1 ampsA
-16.5
VDC @ tbd
600 mA amps
+6.5
VDC @ tbd
1.6 ampsA
-6.5
VDC @ tbd
120 mAamps
Interface: Fiber Optic Ethernet
to M&C and limited front panel operator controls.
B. Mechanical
III. Overview
A. General Description
The L302 is a dual loop phase coherant synthesizer that provides
a leveled 10.8 to 14.8 GHz local oscillator signal at +13 dBm for use in down
conversion. Frequency steps are
essentially continuous, limited only by the tuning resolution of the DDStwo direct digital synthesizer
references. It is a 2-wide with
heatsink module. Four are installed per antenna. The synthesizer is a dual loop design so as to
avoid the use of dividers and preserve phase coherence.
B. Detailed Functional Descriptions
1. RF Signal Flow
Figure
1 RF Block Diagram
C. MIB Interface
The MIB interface to the L302 consists of the SPI bus and associated chip selects and general purpose IO. Refer to Appendix for description of IO functions.
D. Software Control Description
1. Frequency Lock Routine
When a frequency command greater than 1 MHz different from the last command is
received, the acquire lines (MACQ, CACQ) are set TBD and an out
of lock indication is displayed. AGC
amplifier voltage is set according to the lookup table on the network. YIG Coarse tuning voltage is set calculated according
to the table and sent to the lower loop coarse tune DAC.frequency and the stored
polynomial coefficients. The Acquire acquire lines are set TBDcleared and the lock status
is checked. A High lock bit indicates
lock.If
the loop is locked, The the FMVn voltage is
read and if it is within tolerance (~2.100VDCC), no further
action is necessary. The upper main loop is locked
similarly. The synthesizer is returned
to Run Mode. If lock does not occur, the software attemps
to find a valid lock by incrementing or decrementing the coarse tuning DAC If the lock(n) voltage is High and the Frequency is
a “High Lock” frequency according to the lookup table, the coarse tune DAC is
decremented, according to an amount estimated by the difference between the
lock window voltages and the actual voltage.
Acquire lines are set during this function, and “Unlock” indications are
displayed. After acquire lines are
released, the FM voltage is read again.
This sequence continues until the FM Voltage is within tolerance. Similarly, if the lock voltage is low, and
the frequency is a “High Lock” frequency, the DAC is incremented. If the lock voltage is high and the
frequency is a “Low Lock” frequency, the DAC is incremented. If the lock voltage is low and the frequency
is a “Low Lock” frequency, the DAC is incremented down. If the temperature changes n degrees, the DAC
is incremented until the FM voltage is within tolerance. The FM voltage is monitored every n minutes
and the DAC is adjusted as required.
The Lock bit is ignored whenever the acquire bit is set.until lock is found. If lock is found and the FMVn voltage is not
within 2.1V +/- 0.2 volts, the course tune DAC is adjusted to bring it within
tolerance. If lock cannot be found, the
synthesizer reverts to a standby condition.
The failed condition can be determined by examining error messages,
explained in the appendix.
During normal operation, the DDS will be making
changes to the main loop reference, thereby causing the output phase to change. The updates to the DDS cause a momentary out
of lock condition (~40uS) that is ignored by the software.
After the main loop YIG has been coarse tuned and before lock is attempted, the power is adjusted to match the setpoint. This causes the LO level to the comb mixer to be set for optimim power. If the power target cannot be set, the synthesizer reverts to standby.
The synthesizer power out is monitored every TBD minutes and
compared with the value in the lookup table.
The AGC DAC is adjusted to make the monitored voltage equal to the table
value.
2. Dual DDS
The dual DDS supplies
reference signals to the main and control loops Given a linear increase or decrease in frequency, only one DDS changes
frequency. The same algorithm that
determines the DDS frequency also determines the main and control loop
polarities. A
mathcad file is supplied HERE to illustrate the
algorithm. This file will not open unless you have
Mathcad installed.
The upper loop DDS (DDS1) is used
to implement the fringing function. If
offsets are greater than a few megahertz,
the FM voltage of the upper loop should be monitored and the coarse tune DAC
adjusted accordingly. The integrator
should not be zeroed during these fine adjustments (ie, ACQ1 or 2 not enabled)
or the synthesizer will lose lock.
Phase coherence is maintained by arming the phase register and updating
the phase on the edge of the 19.2 Hz timing signal. It is possible to write the phase without the presence of the
timing signal, but phase coherence will be lost. Either DDS can be used to fringe. It is suggested that the lower DDS only be tuned in 1 MHz
increments to maintain sanity. The
phase of the fringing DDS is transferred to the synthesizer output directly,
since there is no division in the VCO feedback.The main loop DDS (MDDS)
carries out the frequency and phase offset function necessary for
interferometry. The control loop DDS (CDDS) carries out
the Walsh function, a phase shift applied at predetermined intervals
related to the system 19.2 Hz timing signal.
AGC Amplifier Routine
The synthesizer power out is adjusted to provide +13 dBm by means of the AGC amplifier. The detector voltage is read (AIN1 of the AtoD) and compared to the value stored in the lookup table. Depending on the detector voltage, the AGC DAC is adjusted until the detector (PWR) voltage is within tolerance.
E. Operator Screen
The operator shall have access to the synthesizer
operating status. Output frequency,
lock condition, and error status. The
operator shall have the ability to initialize the synthesizer after
interrogation.
F. Technician Screen
The technician shall give the technician access to
all analog and digital monitor points, but shall not interrupt normal
synthesizer operation.
G. Maintenance Screen
The maintenance screen shall give the technician
access to all analog to digital monitor points. The technician shall have the ability to control all aspects of
synthesizer operation, as well as examine and change the contents of the
synthesizer memory . The technician
shall be able to initiate self - tests and self - calibration routines. The technician shall be able to change or
examine the contents of the cal files and load or upgrade firmware to the
synthesizer. Some ability to graph or
record monitor points shall be included.
IV. Maintenance
A. List of Required Test equipment
Agilent E4419B Power Meter
Agilent 8485A Power Sensor
B. Procedure
1. General Checkout procedure
Whenever the L302 is repaired, it should be exercised thoroughly using one of the following procedures:
a) Bench:
Connect the L302 to the test bench reference signals and power supplies. Establish communications using the test software. Select “Exercise All Functions” and the desired time period. After the test is completed, there should be no errors.
b) Test Rack:
Install the L302 in the test rack. Using the Test Rack Computer, select the appropriate L302 to exercise. After the test, there should be no errors.
Return the L302 to service or spares making the appropriate entry in the maintenance record.
2. Calibration of AGC Loop
The AGC loop must be calibrated whenever the YIG, AGC
amplifier, or any component in the output signal path is changed, including
cables and attenuators, in order to compensate for changes in the path
attenuation and frequency response. The
calibration procedure steps the synthesizer through all of its possible
operating frequencies, measures the output power with an external power meter, adjusts the AGC DAC for the desired
output power and records the results in a file that is accessed by the synthesizer
during operation. During normal operation, the synthesizer queries the file and
sets the AGC DAC accordingly. See
appendix K for an example Look – Up table file.
1. Apply power to the L302 and the test equipment for at least 15 minutes before beginning calibration. Covers should be in place
2.
Apply reference signals to the L302 and connect the Ethernet adapter.
3. Ensure the correct power head calibration table is selected on the power meter. If the table has not been entered into the power meter, enter it now. Zero and calibrate the sensor.
4. Connect the HPIB cable to the power meter and the lab test computer. Establish communication with the L302 and the power meter.
5.
Connect the power sensor directly to the output of the L302 using the an appropriate adapter. Support the power sensor to facilitate the
connection.
6. Begin calibration. After the calibration is complete, store the calibration data in the appropriate location on the network.
7. Mark calibration date and details in the appropriate location on the module.
V. Appendix
A. L302 Monitor and Control Point Definitions (Telnet session)
Figure x shows the L302 monitor and control screen. Most functions of the synthesizer can be controlled from here. It is accessed by telnet or similar program. The screen is accessed by executing the command “get L302.*”. Individual monitor points can be accessed by executing “get L302.[monitor point]. Commands can be executed (where allowed) by “set L302.[command]”. A brief description of the monitor and control points follows.
Figure 21 Telnet
Session Screen
1. L302 Monitor Points
'AGCV' type='analog' value='2.843000'
“AGCV” is the actual voltage that is supplied to the amplifier that controls the output power of the synthesizer. It can read anywhere from 0 to 4.09 volts.
'PWR' type='analog' value='1.740000'
“PWR” indirectly indicates the power output of the
synthesizer. It is a voltage that is
derived from a diode detector in the RF output assembly. The normal value is between 1 and 2 volts,
depending on the RF chassis configuration.
'FMV1' type='analog' value='1.978000'
“FMV1” indicates the FM coil current in the main loop PLL circuitry. When the synthesizer is locked, it will normally read 1.9 to 2.2 volts. Out of lock it can indicate 0 to 4.09 volts.
'FMV2' type='analog' value='1.990000'
“FMV2” indicates the FM coil current in the control loop PLL circuitry. When the synthesizer is locked, it will normally read 1.9 to 2.2 volts. Out of lock it can indicate 0 to 4.09 volts.
'PS_P6_5' type='analog' value='5.016000'
“PS_P6_5” is the positive 5 volt monitor point. It should normally read 5 +/- 0.1 volts.
'PS_P16_5' type='analog' value='14.884999'
“PS_P16_5” is the positive 15 volt monitor point. It normally reads 15 +/- 0.15 volts.
'PS_N16_5' type='analog' value='-15.139999'
“PS_N16_5” is the negative 15 volt monitor point. It normally reads –15 +/- 0/15 volts.
'PS_N6_5' type='analog' value='-5.006000'
“PS_N6_5” is the negative 5 volt monitor point. It normally reads –5 +/- 0.1 volts.
'Yig1DAOut' type='analog' value='0.973000'
“YIG1DAout” is a scaled version of the output of the main loop YIG coarse tuning voltage. To get the actual voltage, multiply the number by 5.02 to get the actual DAC output voltage
'Yig2DAOut' type='analog' value='0.997000'
“YIG2DAout”
is a scaled version of the output of the control loop YIG coarse tuning
voltage. To get the actual voltage,
multiply the number by 5.02 to get the actual DAC output voltage
'Spare2' type='analog' value='0.004000'
“Spare2” is a spare analog monitor point. It is available on the mother board as an input labeled “AIN 10”. It is divided by 2 and is limited to positive 0 to 8 volts.
'SinkTemp' type='analog' value='27.500000'
“SinkTemp” is a digital monitor point. The temperature sensor is located on the YIG
driver board and is representative of the temperature of the module heat
sink. It reads in Celsius
'YigTemp' type='analog' value='0.000000'
“YIGTemp” is not used.
'MonBrdTemp' type='analog' value='30.750000'
“MonBrdTemp” is the temperature of the monitor board. It represents the general temperature of the right side of the module. It reads in Celsius.
'MainFreq' type='analog' value='22.000000'
“MainFreq” is the frequency of the main loop DDS output. It is not a true read back, it is a command echo. It will read anywhere from 22 to 42 depending on the synthesizer output frequency. It reads in units of Megahertz.
'MainPhase' type='analog'
value='0.000000'
“MainPhase” is the relative phase of the main loop DDS output in relation to the control loop DDS output. It’s value is between 0 and 1 and is multiplied by 360 to obtain degrees. It is a command echo only.
'MainRamp'
type='analog' value='0.000000'
“MainRamp” is a frequency ramp value. It is a command echo only.
'CtrlFreq'
type='analog' value='22.000000'
“CtrlFreq” is the frequency of the control loop DDS output. It is not a true read back, it is a command echo. It will read anywhere from 1 to 22 depending on the synthesizer output frequency. It reads in units of Megahertz.
'LOCK1'
type='digital' value='1'
“LOCK1” is the lock status of the main loop PLL. “1”
indicates lock.
'LOCK2' type='digital' value='1'
“LOCK2” is the lock status of the control loop PLL. “1” indicates lock.
2. L302 Control Points
'AGCV_DAC'
type='analog' value='5.558000'
“AGCV_DAC” is the commanded value of the AGC D to A
converter.
'YIG1_DAC' type='analog' value='4.858727'
“YIG1_DAC” is the commanded value of the main loop YIG
coarse tune D to A converter. It can be
commanded from 0 to 9.99 volts.
'YIG2_DAC' type='analog' value='5.013214'
“YIG2_DAC” is the commanded value of the control loop
YIG coarse tune D to A converter. It
can be commanded from 0 to 9.99 volts.
'LO_FREQ1' type='analog' value='12800.000000'
“LO_FREQ1” is the commanded synthesizer output
frequency. It can be set to any value
between 10800 and 14800.
'LO_FREQ2' type='analog' value='12822.000000'
“LO_FREQ2” is the control loop output frequency. It is an internal software echo and cannot
be set.
'MAIN_PARAMS' type='analog' value='0.000000'
“MAIN_PARAMS” is the control point where the main YIG
tuning parameters are set.
'CTRL_PARAMS' type='analog' value='0.000000'
“CTRL_PARAMS” is the control point where the control
YIG tuning parameters are set.
'PWR_PARAM' type='analog' value='0.000000'
“PWR_PARAM” is the control point where the target PWR value is set. It normally reads 0, unless set to some value. If the MIB is rebooted, it will read 0 again, but the actual value can be accessed by executing a “get L302.pwr.*”.
'RAMP' type='analog' value='0.000000'
“RAMP” controls the frequency ramping rate of the main
DDS.
'PHASE' type='analog' value='0.000000'
“PHASE” controls
the phase of the main loop DDS. It can
be any value between 0 and 1.
'REF_TIME' type='analog' value='0.000000'
I have no clue what this does.
'WALSH_SEED' type='analog' value='0.000000'
“WALSH_SEED” enables Walsh switching. A value of –1 cause the output phase to
switch 180 degrees every 52mS.
'WALSH_OFFSET' type='analog' value='0.000000'
Once again, I have no clue what this does.
'STANDBY' type='digital' value='0'
“STANDBY” indicates the standby status of the
synthesizer. In normal operation, it
will be “0”. Conditions that can cause
standby are inability to find lock, unable to reach the specified power output
value, among others.
'POLARITY' type='digital' value='0'
“POLARITY” controls the output polarity of the main
loop PLL. It can be either 0 or 1
depending on the frequency of the synthesizer.
Commanding this point to a value other than the one that is displayed
will cause the synthesizer to lose lock and to execute a find lock routine, unless
it is in standby.
'POLARITY2' type='digital' value='1'
“POLARITY2” controls the output polarity of the
control loop PLL. It can be either 0 or
1 depending on the frequency of the synthesizer. Commanding this point to a value other than the one that is
displayed will cause the synthesizer to lose lock and to execute a find lock
routine, unless it is in standby.
'INT_ZERO' type='digital' value='0'
“INT_ZERO” causes the main loop integrator to
discharge, allowing coarse tuning without any FM coil current. Commanding this point to a value other than
the one that is displayed will cause the synthesizer to lose lock and to
execute a find lock routine, unless it is in standby.
'INT_ZERO2' type='digital' value='0'
“INT_ZERO2” causes the control loop integrator to
discharge, allowing coarse tuning without any FM coil current. Commanding this point to a value other than
the one that is displayed will cause the synthesizer to lose lock and to
execute a find lock routine, unless it is in standby.
B. Frequently Used Commands. (Telnet session)
Several synthesizer parameters can be manipulated to determine faults or to optimize operation of the synthesizer. Summarized here are a few of those commands. Commands are not case sensitive. To execute these commands via telnet, open a telnet session and set the local echo on by typing “set local_echo”. This will allow you see the commands that are enetered during the telnet session. After local echo is set, type “open evla-mib-xx” or, if the synthesizer is installed in the antenna “open EA14-L302-1”. This will change, of course, depending on which antenna and which synthesizer you desire to command.
“get L302.*”
Causes all the monitor and control points to be echoed on screen.
“set L302.mib.reboot=1”
Causes the MIB to reboot and terminates the telnet session. Use this when things have really gone wrong and you want to start from a known state.
“get l302.*.msg”
If the synthesizer is in standby, this command is useful in determining at what point in the software routine where the error occurred.
“set L302.LO_FREQ1”
This command sets the synthesizer output frequency. It causes the synthesizer to revert from standby, if it was in standby, and attempt to find lock at the new frequency. If this command is identical to the last commanded frequency, nothing will happen. Changes in frequency less than 1 MHz do not initiate AGC setting, or find lock routines. Lock should normally occur within 1 second regardless of frequency change.
“set L302.pwr_param= x.xx”
This command changes the stored value that causes the
synthesizer to adjust it’s power output to match the value entered. The value will typically be between 1 and 2
volts. Normally this is done with the
synthesizer on the bench attached to a power meter. The calibration of this value is normally done automatically
during calibration of the synthesizer.
Before altering this value, the original target value should be recorded
by executing a “get L302.pwr.*” command.
There is no direct relation to this value and the power output of the synthesizer,
it must be determined during calibration.
The new target value will be used upon the next major frequency change
(>1 MHz). The synthesizer will
revert to standby if it is unable to reach the target value and may or may not
lock. This data is stored in the EEPROM
on board the Monitor / AGC PCB and as such the PCB cannot be swapped among
synthesizers.
“set L302.AGCV_DAC=x.xx”
This command is useful for altering the power out of the synthesizer without setting the power parameter above. It will accept values between 0 and 4.09 volts. This can be adjusted with the synthesizer operating normally as well as in standby. The next major frequency change will overwrite any value entered. This voltage can be adjusted until the power output is at the desired level as indicated on an external power meter. Once this is achieved, the “pwr” monitor point can be examined. The voltage at this monitor point can now be entered into the power parameter above and the output of the synthesizer will be leveled at this frequency. This operation can be performed in normal or standby operation.
“set L302.YIGn_DAC=x.xxx”
This command will adjust the YIG course tuning D to A
converter to the commanded value. When
executed from a standby condition, the DAC will adjust it’s output to the
commanded value and remain. Changes of
more than a few 10’s of mill volts from a locked and normal condition will
cause the lock maintenance routine to be executed or find lock routine to be
executed. The entered value will be over
written by the software routines.
“get L302.LO_FREQn.*”
This monitor point fetch will display the YIG curve
parameters p0, p1, and p2, among other parameters. p0, p1, and p2 are the coefficients of a 2nd degree
polynomial which are determined during calibration. To calculate the proper tuning voltage, the software uses a
formula in which the input is the frequency in MHz and the output is the
voltage desired, i.e.: Vout = p2(F^2) + p1(F) + p0. Only 6 significant digits are displayed, so the p2 term may
appear to be 0, but the actual value is to 12 significant digits. These values can also be set, but unless
absolutely sure, it is not recommended as this could cause the synthesizer to
not lock. This data is stored in the
EEPROM on board the Monitor / AGC PCB and as such the PCB cannot be swapped
among synthesizers.
“get mib.*”
Returns values relevant to software and MIB
hardware. The only relevant points for
maintenance are “moduleversion” and “heartinterval”. Module version should correlate to the
latest revision and heartinterval should show 0.052, indicating presence
of the RS-485 level 52mS timing signal is being received by the MIB. It does not indicate that proper
timing is reaching the DDS.
C. MIB I/O
|
L302 Name |
MIB Name |
MIB Jx-n |
I/O (rel to L302) |
Function |
|
SDO |
MISO |
J5-02 |
O – M&C |
Serial Data Out |
|
SDI |
MOSI |
J5-04 |
I – M&C |
Serial Data In |
|
SCLK |
SCLK |
J5-06 |
I – M&C |
Shift Clock |
|
CSPROM |
|
J5-08 |
I – C |
Select EEPROM |
|
WP |
|
J5-09 |
I – C |
EEPROM Write Protect |
|
CSDAC1 |
|
J5-11 |
I – C |
Select AGC DAC |
|
FS |
|
J5-12 |
I – C |
EEPROM Frame Sync |
|
CSADC1 |
|
J5-14 |
I – C |
Select Monitor A to D |
|
CSMONTEMP |
|
J5-15 |
I – C |
Select Monitor Board Temp |
|
|
|
J5-17 |
I – C |
Not Used |
|
CSHSTEMP |
|
J5-18 |
I – C |
Select Heat Sink Temp |
|
CSDAC |
|
J5-20 |
I – C |
Select YIG Coarse Tune DAC’s (both) |
|
MDACUD |
|
J5-21 |
I – C |
Update Main loop DAC |
|
|
|
J5-23 |
I – C |
Not Used |
|
CDACUD |
|
J5-24 |
I – C |
Update Control loop DAC |
|
DDSCS0 |
|
J5-26 |
I – C |
DDS Chip Select 0 |
|
DDSCS1 |
|
J5-27 |
I – C |
DDS Chip Select 1 |
|
DDSCS2 |
|
J5-29 |
I – C |
DDS Chip Select 2 |
|
DDSCS3 |
|
J5-30 |
I - C |
DDS Chip Select 3 |
|
REFPWR |
|
J4-30, IO19 |
O – M |
128 Reference Power Present |
|
19Hz |
|
J4-32, IO20 |
O – M |
19.2 Hz LVDS Present Signal |
|
MLOCK |
|
J4-33, IO21 |
O – M |
Main Loop Lock Status (1 = Lock) |
|
CLOCK |
|
J4-35, IO22 |
O - M |
Control Loop Lock Status ( 1 = Lock) |
|
EOC |
|
J4-36, IO23 |
O - M |
A to D EOC Flag |
|
MPOL |
|
J4-38, IO24 |
I – C |
Main Loop PLL Polarity Control |
|
MACQ |
|
J4-39, IO25 |
I – C |
Main Loop integrator zero |
|
CACQ |
|
J4-41, IO26 |
I – C |
Control Loop integrator zero |
|
CTRSEL |
|
J4-42, IO27 |
I – C |
Microwave Prescaler input select |
|
CPOL |
|
J4-44, IO 28 |
I – C |
Control Loop PLL Polarity Control |
|
PPDN |
|
J4-45, IO29 |
|
Prescaler Power Down |
D. Analog to Digital Converter Channel Assignments
|
A to D Channel |
Name |
Signal |
Display Factor |
Update freq. (s) |
Archive |
|
AIN0 |
AGCV |
AGC Voltage |
*1 |
As req’d |
N |
|
AIN1 |
PWR |
Synth Power Out (Detector Voltage) |
*1 |
As Req’d |
N |
|
AIN2 |
FMV1 |
PLL1 FM Voltage |
*1 |
As Req’d |
N |
|
AIN3 |
FMV2 |
PLL2 FM Voltage (L302 only) |
*1 |
As Req’d |
N |
|
AIN4 |
PS65 |
+6.5 Volt Supply |
*2 |
As Req’d |
Y |
|
AIN5 |
PS165 |
+16.5 Volt Supply |
*5 |
As Req’d |
Y |
|
AIN6 |
NS165 |
-16.5 Volt Supply |
*-5 |
As Req’d |
Y |
|
AIN7 |
NS65 |
-6.5 Volt Supply |
*-2 |
As Req’d |
Y |
|
AIN8 |
MCoarseV |
Coarse Tuning Voltage |
*5.02 |
As Req’d |
N |
|
AIN9 |
CCourseV |
Coarse Tuning Voltage (L302 only) |
*5.02 |
As Req’d |
N |
|
AIN10 |
SPARE |
Spare Input 2:1 |
*2 |
As Req’d |
N |
Table 2 Analog to Digital Converter channels
E. TLV2556 (11 Channel, 12 BIT, Analog to Digital Converter) Control Lines
This A to D converter is responsible for monitoring analog voltages. The internal 4.096 volt reference is used. Refer to Texas Instruments Data Sheet for detailed Information.
|
Signal Name |
MIB I/O |
Function |
Remarks |
|
SCLK |
SCLK |
Shift Clock |
Refer to data sheet |
|
SDI |
MOSI |
Serial Data in |
Refer to data sheet |
|
SDO |
MISO |
Serial Data out |
Refer to data sheet |
|
CS |
CSADC1 |
Chip Select |
Active Low |
|
EOC |
EOC |
End of Conversion Flag |
Refer to data sheet |
|
|
|
|
|
Table 3 Monitor Analog to Digital Converter Control Lines
F. DAC716, 16 Bit Digital to analog converter control lines.
This D to A converter controls the coarse tuning of the YIG oscillator. The internal 10.000 volt reference is used. Refer to Texas Instruments Data Sheet for detailed information.
|
Signal Name |
MIB I/O |
Function |
Remarks |
|
SCLK |
SCLK |
Shift Clock |
Refer to data sheet |
|
SDI |
MOSI |
Serial Data In |
Refer to data sheet |
|
SDO |
MISO |
Serial Data Out |
NOT CONNECTED |
|
A0 |
CSDACn |
Shift Register Control |
Input Shift register |
|
A1 |
DACnUD |
Update DAC Output |
D/A Latch |
Table 4 Coarse Tuning Digital to Analog Converter Control Lines
G. MAX6629 Temperature Sensor Control Lines
These sensors measure the temperature of the module in two locations, on the monitor board and heat sink. Refer to Maxim Data Sheet for detailed Information
|
Signal Name |
MIB I/O |
Function |
Remarks |
|
SCLK |
SCLK |
Shift Clock |
Refer to data sheet |
|
SDO |
MISO |
Serial Data Out |
Refer to data sheet |
|
CS |
CSTEMPn |
Chip Select |
Refer to data sheet |
Table 5 Temperature Sensor Control Lines
H. Atmel AT25256 256K Serial EEPROM Control Lines
This EEPROM contains various module specific information. Refer to Atmel Data Sheet for detailed Information.
|
Signal Name |
MIB I/O |
Function |
Remarks |
|
SCLK |
SCLK |
Shift Clock |
Refer to data sheet |
|
SDI |
MOSI |
Serial Data In |
Refer to data sheet |
|
SDO |
MISO |
Serial Data Out |
Refer to data sheet |
|
CS |
CSPROM |
Chip Select |
Active Low |
|
WP |
WP |
Write Protect |
Hardware jumper only |
I. TLV5624 Texas Instruments 8 Bit D to A Converter (AGC DAC)
This D to A converter controls the gain controlled output leveling amplifier. Refer to Texas Instruments Data Sheet for detailed information.
|
Signal Name |
MIB I/O |
Function |
Remarks |
|
SCLK |
SCLK |
Shift Clock |
Refer to data sheet |
|
SDI |
MOSI |
Serial Data In |
Refer to data sheet |
|
SDO |
MISO |
Serial Data Out |
Refer to data sheet |
|
FS |
FS |
Frame Sync |
Refer to data sheet |
Table 7 AGC D to A Converter Control Lines
J. AD9852 Analog Devices DDS
The DSS generates reference signals for the phase locked loop and is used for fringing. Refer to AD9852 Data Sheet for detailed information.
|
Signal Name |
MIB I/O |
Function |
Remarks |
|
DDSCS0 |
DDSCS1 |
Control Register |
|
|
DDSCS1 |
DDSCS2 |
AD9852 #1 (DDS1) |
|
|
DDSCS2 |
DDSCS3 |
AD9852 #2 (DDS2) |
|
|
DDSCS3 |
DDSCS4 |
Counter Register |
|
|
DDSCS4 |
DDSCS5 |
Counter Register |
|
Table 8 AD9852 DDS Control Lines
K. Example of EEPROM stored Data (ASCII)
Build Date
YIG Model, serial