wbc-
   attributes-
	
	time- (dateTime) returned as part of acknowledgement (R only)

	delayTapCal- (ready/notReady)  state of the input delay tap calibration (R only)

	inputPhaseAdjust0 - (stop/run) base band 0 input delay is adjusting (run) or not (stop) (R only)

	inputPhaseAdjust1 - (stop/run) base band 1 input delay is adjusting (run) or not (stop) (R only)

	sysClockLock - (lock/free)  state of SCLK (R only)

	standby - (off/on)  global clocking disable ("on" saves power) (R/W)

	programEnable - (yes/no)  enable/disable FPGA reprogramming (R/W)

	reset - (no argument required) resets FPGA to default register contents (W only)

	ticCount0 - (0-4194303) value of time interval counter on input 0 (R only)

	ticCount1 - (0-4194303) value of time interval counter on input 1 (R only)


	elements-
		
	inOut- (none or one element only)
		attributes-
		
			fineDelay0- (0-4992) input 0 delay in units of picoseconds (R/W)

			fineDelay1- (0-4992) input 1 delay in units of picoseconds (R/W)
			
			crcCheckBit0- (0-63) input 0 bit to generate CRC from (R/W)

			crcCheckBit1- (0-63) input 1 bit to generate CRC from (R/W)

			crc0- (0-15) CRC generated on input 0 selected bit (R only)

			crc1- (0-15) CRC generated on input 1 selected bit (R only)

			numBands- (1-16) number of bands in wideband input (R/W)

			numBits- (1-8) number of bits used in wideband input samples (R/W)

			inRate- (enumerated, see xsd file) input data rate (R/W)

			outRate- (enumerated, see xsd file) input data rate (R/W)

	testPin- (none to four elements only)
		 attributes-

			id- (0-3) test pin corresponding to signal attribute (R/W)
			
			signal (0-31) internal signal to route to test pin (R/W)

	products- (none to four elements only)
		  attributes-

			id- (0-3) product buffer to use (R/W)

			reset- (no argument required) discontinue use of specified buffer (W only)

			promptPath- (0-1) wide band input number to feed "prompt" data path (R/W)

			laggedPath- (0-1) wide band input number to feed "lagged" data path (R/W)

			promptBand- (1-16) input band number to feed "prompt" data path (R/W)

			laggedband- (1-16) input band number to feed "lagged" data path (R/W)

			endLag- (63-32767) last lag (or total number of lags) to collect for this product buffer (R/W)

	register- (none to infinite elements)
		  attributes-
		  
			address- (0-255 in hex, octal, or decimal) register address to set (R/W)
			
			value-(0-2^32 in hex, octal, or decimal) data to fill register specified in address (R/W)
			
	user- (none to one elements only)
		  attributes-

			logLevel- (enumerated, see xsd file) minimum log level to write to log (R/W)

			logPipe- (off/on) state of log message flow (R/W)

			logFile- (local filename) file to write log messages into

	about- (none to one element)
		  attributes-
		  
			fpgaVersion- (0-15) "version" tag from module (R only)
			
			fpgaRevision- (0-15) "revision" tag from module (R only)
			
			functionType- (0-255) "type" tag from module (R only)

			driverVersion- (major#<dot>minor#) version of module driver code. (R only)

			status- (arbitrary string) general module status (TBD) (R only)

	error- (none to many)
	       <TBD>

	       
	state- (none to one element)
	          attributes-
		  
			inOut- (no argument required) report the complete "inOut" element state (W only)

			products- (no argument required) report all "products" element states (W only)

			testPin- (no argument required) report all "testPin" element states (W only)

			register- (no argument-> return all registers, address->return single register contents) (W only)

			user- (no argument required) report the complete "user" element state (W only)

			about- (no argument required) report the complete "about" element state (W only)

			error- <TBD>