Enter: Address only to GET, Address + Value to SET.
Addr Value
(all values assumed to be Hex)
Baseline Board Device Map
PCMC FPGA 0000 Ethernet Chip 0100 Correlator X0Y0 4000 Y1 4100 Y2 4200 Y3 4300 Y4 4400 Y5 4500 Y6 4600 Y7 4700 Correlator X1Y0 4800 Y1 4900 Y2 4a00 Y3 4b00 Y4 4c00 Y5 4d00 Y6 4e00 Y7 4f00 Correlator X2Y0 5000 Y1 5100 Y2 5200 Y3 5300 Y4 5400 Y5 5500 Y6 5600 Y7 5700 Correlator X3Y0 5800 Y1 5900 Y2 5a00 Y3 5b00 Y4 5c00 Y5 5d00 Y6 5e00 Y7 5f00 Correlator X4Y0 6000 Y1 6100 Y2 6200 Y3 6300 Y4 6400 Y5 6500 Y6 6600 Y7 6700 Correlator X5Y0 6800 Y1 6900 Y2 6a00 Y3 6b00 Y4 6c00 Y5 6d00 Y6 6e00 Y7 6f00 Correlator X6Y0 7000 Y1 7100 Y2 7200 Y3 7300 Y4 7400 Y5 7500 Y6 7600 Y7 7700 Correlator X7Y0 7800 Y1 7900 Y2 7a00 Y3 7b00 Y4 7c00 Y5 7d00 Y6 7e00 Y7 7f00 LTA X0Y0 8000 Y1 8100 Y2 8200 Y3 8300 Y4 8400 Y5 8500 Y6 8600 Y7 8700 LTA X1Y0 8800 Y1 8900 Y2 8a00 Y3 8b00 Y4 8c00 Y5 8d00 Y6 8e00 Y7 8f00 LTA X2Y0 9000 Y1 9100 Y2 9200 Y3 9300 Y4 9400 Y5 9500 Y6 9600 Y7 9700 LTA X3Y0 9800 Y1 9900 Y2 9a00 Y3 9b00 Y4 9c00 Y5 9d00 Y6 9e00 Y7 9f00 LTA X4Y0 a000 Y1 a100 Y2 a200 Y3 a300 Y4 a400 Y5 a500 Y6 a600 Y7 a700 LTA X5Y0 a800 Y1 a900 Y2 aa00 Y3 ab00 Y4 ac00 Y5 ad00 Y6 ae00 Y7 af00 LTA X6Y0 b000 Y1 b100 Y2 b200 Y3 b300 Y4 b400 Y5 b500 Y6 b600 Y7 b700 LTA X7Y0 b800 Y1 b900 Y2 ba00 Y3 bb00 Y4 bc00 Y5 bd00 Y6 be00 Y7 bf00 Recirc Y0 c000 Y1 c100 Y2 c200 Y3 c300 Y4 c400 Y5 c500 Y6 c600 Y7 c700 Recirc X0 c800 X1 c900 X2 ca00 X3 cb00 X4 cc00 X5 cd00 X6 c600 X7 cf00